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| DP80C51 Pipelined High Performance 8-bit Microcontroller ver 4.01 OVERVIEW DP80C51 is an ultra high performance, speed optimized soft core of a single-chip 8bit embedded controller dedicated for operation with fast (typically on-chip) and slow (offchip) memories. The core has been designed with a special concern for performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU. DP80C51 soft core is 100% binary and pin compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of the DP80C51: Harward, where external data and program buses are separated, and von Neumann, with common program and external data bus. DP80C51 has Pipelined RISC architecture up to 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slower than the original implementation for no performance penalty. DP80C51 is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow. CPU FEATURES 100% pin compatible with industry standard 8051 100% software compatible with industry standard 8051 Pipelined RISC architecture enables to execute instructions up to 10 times faster compared to standard 8051 24 times faster multiplication 12 times faster addition Up to 256 bytes of internal (on-chip) Data Memory Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory Up to 64K bytes of external (off-chip) Data Memory User programmable Program Memory Wait States solution for wide range of memories speed User programmable External Data Memory Wait States solution for wide range of memories speed Dedicated signal for Program Memory writes. Interface for additional Special Function Registers All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states Scan test ready 2.0 GHz virtual clock frequency in a 0.25u technological process Synchronous mode, fixed baud rate 8-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, variable baud rate CONFIGURATION The following parameters of the DP80C51 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. * * * Internal Program Memory type Internal Program ROM Memory size Internal Program RAM Memory size - synchronous - asynchronous 0 - 64kB 0 - 64kB subroutines location PERIPHERALS DoCDTM debug unit Processor execution control Run Halt Step into instruction Skip instruction Read-write all processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Code execution breakpoints one real-time PC breakpoint unlimited number of real-time OPCODE breakpoints Hardware execution watch-point one at Internal (direct) Data Memory one at Special Function Registers (SFRs) one at External Data Memory Hardware watch-points activated at a certain address by any write into memory address by any read from memory address by write into memory a required data address by read from memory a required data Unlimited number of software watch-points Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Unlimited number of software breakpoints Program Memory(PC) Automatic adjustment of debug data transfer * Interrupts * Power Management Mode * Stop mode * DoCDTM debug unit - used - unused - used - unused - used - unused Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file. speed rate between HAD and Silicon JTAG Communication interface Power Management Unit Power management mode Switchback feature Stop mode Interrupt Controller 2 priority levels 2 external interrupt sources 3 interrupt sources from peripherals Four 8-bit I/O Ports Bit addressable data direction for each line Read/write of single line and 8-bit group Two 16-bit timer/counters Timers clocked by internal source Auto reload 8-bit timers Externally gated event counters Full-duplex serial port http://www.DigitalCoreDesign.com http://www.dcd.pl All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment NCSim automatic simulation macros ModelSim automatic simulation macros Active-HDL automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance DESIGN FEATURES PROGRAM MEMORY: The DP80C51 soft core is dedicated for operation with Internal and External Program Memory. Internal Program Memory can be implemented as: ROM located in address range between 0x0000 / (ROMsize-1) RAM located in address range between External Program Memory can be implemented as ROM or RAM located in address range between ROMsize / RAMsize. INTERNAL DATA MEMORY: The DP8C051 can address Internal Data Memory of up to 256 bytes The Internal Data Memory can be implemented as Single-Port synchronous RAM. EXTERNAL DATA MEMORY: The DP80C51 soft core can address up to 64 kB of External Data Memory. USER SPECIAL FUNCTION REGISTERS: Up to 104 External (user) Special Function Registers (ESFRs) may be added to the DP80C51 design. ESFRs are memory mapped into Direct Memory between addresses 0x80 and 0xFF in the same manner as core SFRs and may occupy any address that is not occupied by a core SFR. WAIT STATES SUPPORT: The DP80C51 soft core is dedicated for operation with wide range of Program and Data memories. Slow Program and External Data memory may assert a memory WAIT signal to hold up CPU activity for required period of time. (RAMsize-1) / 0xFFFF Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows using IP Core in single FPGA bitstream and ASIC implementation. It also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time of use limitations. Single Design license for VHDL, Verilog source code called HDL Sour- ce Encrypted, or plain text EDIF called Netlist Unlimited Designs license for HDL Source Netlist Upgrade from Netlist to HDL Source Single Design to Unlimited Designs All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. SYMBOL port0(7:0) port1(7:0) port2(7:0) port3(7:0) ale psen pswr prgaddr(15:0) prgdatao(7:0) prgramwr ramaddr(7:0) ramdatao(7:0) ramwe ramoe sfraddr(6:0) sfrdatao(7:0) sfroe sfrwe stop pmm tdi tck tms reset clk tdo rtck coderun debugacs rsto PIN port3[5] port3[6] port3[7] ea prgramdatai[7:0] prgromdatai[7:0] ramdatai[7:0] sfrdatai[7:0] tdi tck tms rsto prgaddr[15:0] prgdatao[7:0] prgramwr ale psen pswr ramaddr[7:0] ramdatao[7:0] ramoe ramwe sfraddr[6:0] sfrdatao[7:0] sfroe sfrwe tdo rtck debugacs coderun pmm stop TYPE bidir bidir bidir input input input input input input input input DESCRIPTION I/O Port 3.5, multifunctional Timer 1 external clock line I/O Port 3.6 External Data Memory write I/O Port 3.7 External Data Memory read Enable all external program memory Data bus from int. RAM prog. memory Data bus from int. ROM prog. memory Data bus from internal data memory Data bus from user SFR's DoCDTM TAP data input DoCDTM TAP clock input DoCDTM TAP mode select input ea prgromdatai(7:0) prgramdatai(7:0) ramdatai(7:0) output Reset output output Internal program memory address bus output Data bus for internal program memory output Internal program memory write output Address Latch Enable output Program Store (memory) read Enable output Program Store (memory) Write output Internal Data Memory address bus output Data bus for internal data memory output Internal data memory output enable output Internal data memory write enable output Address bus for user SFR's output Data bus for user SFR's output User SFR's read enable output User SFR's write enable output DoCDTM TAP data output output DoCDTM return clock line output DoCDTM accessing data output CPU is executing an instruction output Power management mode indicator output Stop mode indicator sfrdatai(7:0) PINS DESCRIPTION PIN clk reset port0[7:0] port1[7:0] port2[7:0] port3[0] port3[1] port3[2] port3[3] port3[4] TYPE input input bidir bidir bidir bidir bidir bidir bidir bidir DESCRIPTION Global clock Global reset input I/O Port 0, multifunctional Data/LSB address of external memory I/O Port 1 I/O Port 2, multifunctional MSB address of external memory I/O Port 3.0 Serial receiver input/output port I/O Port 3.1 Serial transmitter output port I/O Port 3.2, multifunctional Interrupt 0 input/timer 0 gate I/O Port 3.3, multifunctional Interrupt 1 input/timer 1 gate I/O Port 3.4, multifunctional Timer 0 external clock line All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. BLOCK DIAGRAM Opcode decoder prgramdatai(7:0) prgromdatai(7:0) prgaddr(15:0) prgdatao(7:0) prgramwr I/O Port registers port0(7:0) port1(7:0) port2(7:0) port3(7:0) EEPROM storage via UART, SPI, I2C or DoCDTM module. External Memory Interface - Contains memory access related registers such as Data Page High (DPH), Data Page Low (DPL). It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories. Internal Data Memory Interface - Internal Data Memory interface controls access into the internal 256 bytes memory. It contains 8-bit Stack Pointer (SP) register and related logic. stop pmm Program memory interface Timers ea ale psen pswr UART External memory interface Interrupt controller Control Unit ramaddr(7:0) ramdatao(7:0) ramdatai(7:0) ramwe ramoe sfraddr(6:0) sfrdatao(7:0) sfrdatao(7:0) sfroe sfrwe clk reset rsto Power Management Unit Internal data memory interface DoCDTM Debug Unit User SFR's interface ALU tdi tck tms tdo rtck coderun debugacs User SFRs Interface - Special Function Registers interface controls access to the special registers. It contains standard and used defined registers and related logic. User defined external devices can be quickly accessed (read, written, modified) using all direct addressing mode instructions. Interrupt Controller - Interrupt control module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers. Note that external pins of this module are connected to appropriate pins of P3 port. Timers - System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 CLK periods when appropriate timer is enabled. In the counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock sources for UARTs. Note that external pins of this module are connected to appropriate pins of P3 port. UART0 - Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to http://www.DigitalCoreDesign.com http://www.dcd.pl UNITS SUMMARY ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit, logic unit, multiplier and divider. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. Control Unit - Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks. Program Memory Interface - Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new program into RAM, EPROM or FLASH All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1. Note that external pins of this module are connected to appropriate pins of P3 port. Ports - Block contains 8051's general purpose I/O ports. Each of port's pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3. The P0, P2, P3 are multifunctional ports. When used with External memory P0 works as a multiplexed Data/LSB address to memory, and P2 works as a MSB address to external memory, P3.6 is a write signal and P3.7 is a read signal. Functionality of port is the same as in legacy 80C51 microcontroller. Power Management Unit - Block contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when microcontroller is planned to use in portable and power critical applications. DoCDTM Debug Unit - it's a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other onchip debuggers DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. Two additional pins CODERUN, DEBUGACS indicate the sate of the debugger and CPU. CODERUN is active when CPU is executing an instruction. DEBUGACS pin is active when any access is performed by DoCDTM debugger. The DoCDTM system includes JTAG interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been All trademarks mentioned in this document are trademarks of their respective owners. taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. PROGRAM CODE SPACE IMPLEMENTATION The figure below shows an example Program Memory space implementation in systems with DP80C51 Microcontroller core. The On-chip Program Memory located in address space between 0kB and 1kB is typically used for BOOT code with system initialization functions. This part of the code is typically implemented as ROM. The On-chip Program Memory located in address space between 60kB and 64kB is typically used for timing critical part of the code e.g. interrupt subroutines, arithmetic functions etc. This part of the code is typically implemented as RAM and can be loaded by the BOOT code during initialization phase from Off-chip memory or through RS232 interface from external device. From the two mentioned above spaces program code is executed without wait-states and can achieve a top performance up to 200 million instructions per second (many instructions executed in one clock cycle). The Off-chip Program Memory located in address space between 1kB and 60kB is typically used for main code and constants. This part of the code is usually implemented as ROM, SRAM or FLASH device. Because of relatively long access time the program code executed from mentioned above devices must be fetched with additional Wait-States. Number of required Wait-States depends on memory access time and DP80C51 clock frequency. 0xFFFF 0xF000 On chip Memory (implemented as RAM) Off chip Memory (implemented as ROM, SRAM or FLASH) 0x0400 0x0000 On-chip Memory (implemented as ROM) http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. In most cases the proper number of WaitStates cycles is between 2-5. The READY pin can be also dynamically modulated e.g. by SDRAM controller. The figure below shows a typical Program Memories connections in system with DP80C51 Microcontroller core. prgramdatai prgdatao prgramwr prgaddr 10 prgromdatai 8 ASIC or FPGA chip 8 Latch STRATIX STRATIX-II -5 -3 90 MHz 160 MHz Core performance in ALTERA(R) devices 8 8 12 On-chip Memory (implemented as RAM) 0 Wait-State access For a user the most important is application speed improvement. The most commonly used arithmetic functions and theirs improvement are shown in table below. Improvement was computed as {80C51 clock periods} divided by {DP80C51 clock periods} required to execute an identical function for code executed from internal (first column) and external (second column) program memory. More details are available in core documentation. Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 32-bit subtraction 32-bit multiplication Average speed improvement: Improvement 9,00 3,00 9,00 3,00 9,00 3,60 12,00 4,00 9,00 3,00 9,00 3,00 9,00 3,60 12,00 4,00 16,00 6,00 9,60 4,80 12,00 4,00 12,00 4,00 13,60 5,47 12,00 4,00 12,00 4,00 12,60 4,89 11,12 4,03 On-chip Memory (implemented as ROM) 0 Wait-State access DP80C51 port0 ale port2 psen pswr Off-chip Memory (implemented as FLASH, or SRAM) eg. 2-5 Wait-State access 8 The described above implementation should be treated as an example. All Program Memory spaces are fully configurable. For timing-critical applications whole program code can be implemented as on-chip ROM and (or) RAM and executed without Wait-States, but for some other applications whole program code can be implemented as off-chip ROM or FLASH and executed with required number Wait-State cycles. Dhrystone Benchmark Version 2.1 was used to measure Core performance. The following table gives a survey about the DP80C51 performance in terms of Dhrystone/sec and VAX MIPS rating for testing code executed from external (1) and internal (2) program memory. Device 80C51 80C310 DP80C511 2 DP80C51 Target STRATIX-II STRATIX-II Clock frequency 12 MHz 33 MHz 150 MHz 150 MHz Dhry/sec (VAX MIPS) 268 (0.153) 1550 (0.882) 11525 (6,563) 26220 (14.924) PERFORMANCE The following tables give a survey about the Core area and performance in Programmable Logic Devices after Place & Route (CPU features and peripherals have been included): Device FLEX10KE ACEX1K APEX20K APEX20KE APEX20KC APEX-II MERCURY CYCLONE CYCLONE-II Speed grade -1 -1 -1 -1 -7 -7 -5 -6 -6 Fmax 57 MHz 57 MHz 50 MHz 66 MHz 78 MHz 76 MHz 100 MHz 91 MHz 93 MHz Core performance in terms of Dhrystones All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. 28000 26000 24000 22000 20000 18000 16000 14000 12000 10000 8000 6000 4000 2000 0 26220 11525 268 1550 80C51 (12MHz) 80C310 (33MHz) DP80C51 - external program memory (150MHz) DP80C51 - internal program memory (150MHz) Area utilized by the each unit of DP80C51 core in vendor specific technologies is summarized in table below. Component CPU* Interrupt Controller Power Management Unit I/O ports Timers UART0 Total area Area [LC] [FFs] 1670 150 10 100 160 210 2300 310 40 5 35 50 60 500 *CPU - consisted of ALU, Opcode Decoder, Control Unit, Program & Internal & External Memory Interfaces, User SFRs Interface Core components area utilization in all technologies except STRATIX-II Component CPU* Interrupt Controller Power Management Unit I/O ports Timers UART0 Total area Area [LC] [FFs] 1305 115 10 75 125 160 1790 310 40 5 35 50 60 500 *CPU - consisted of ALU, Opcode Decoder, Control Unit, Program & Internal & External Memory Interfaces, User SFRs Interface Core components area utilization in STRATIX-II All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. The main features of each DP80C51 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Architecture speed grade Program Memory space Stack space size on-chip ROM on-chip RAM Power Management Unit Internal Data Memory space External Data Memory space External Data / Program Memory Wait States Compare/Capture Interrupt sources Interface for additional SFRs Timer/Counters Interrupt levels Master I2C Bus Controller Slave I2C Bus Controller Data Pointers Design DP8051CPU DP8051 DP8051XP 10 10 10 64k 64k 64k 256 256 16M 64k 64k 64k 256 256 16M 64k 64k 64k 256 256 16M 2 5 15 2 2 2 1 1 2 2 3 1 2 4 4 - - - - - DP8051 family of Pipelined High Performance Microcontroller Cores The main features of each DP80390 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Architecture speed grade Program Memory space Stack space size on-chip ROM on-chip RAM Power Management Unit Internal Data Memory space External Data Memory space External Data / Program Memory Wait States Compare/Capture Interrupt sources Interface for additional SFRs Timer/Counters Interrupt levels Master I C Bus Controller Slave I2C Bus Controller Data Pointers Design off-chip DP80390CPU DP80390 DP80390XP 10 10 10 64k 64k 8M 256 256 16M 64k 64k 8M 256 256 16M 64k 64k 8M 256 256 16M 2 5 15 2 2 2 1 1 2 2 3 1 2 4 4 - - - - - DP80390 family of Pipelined High Performance Microcontroller Cores All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Fixed Point Coprocessor Floating Point Coprocessor - Watchdog I\O Ports UART 2 SPI Fixed Point Coprocessor Floating Point Coprocessor - Watchdog I\O Ports off-chip UART SPI CONTACTS For any modification or special request contact to DCD. Headquarters: Wroclawska 94 41-902 Bytom, POLAND nfo@dcd.pl e-mail: iinfo@dcd.pl tel. fax : +48 32 282 82 66 : +48 32 282 74 37 Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. |
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